1. Field of the Invention
The present invention relates to On-Chip network; and, more particularly, to a slave network interface circuit for improving the parallelism of an On-Chip network having a slave network interface at each slave module for improving the parallelism of data communication between master modules and slave modules, and a system thereof.
This work was supported by the Information Technology (IT) research and development program of the Korean Ministry of Information and Communication (MIC) and/or the Korean Institute for Information Technology Advancement (IITA) [2005-S-077-02, “Development of On-Chip Network Based SoC Platform”].
2. Description of Related Art
According to the development of a semiconductor fabricating technology, a system on chip (SoC) design was introduced. The SoC design is a technology for integrating a processor, a memory, and peripheral devices into a single chip. The goal of the SoC design is to make single chip to perform various functions by integrating verified intellectual properties (IP) in single chip. The IP generally stands for an intellectual property such as patent. In semiconductor field, the IP particularly means a semiconductor design module that is a functional block having an independent function and reusable in semiconductor integrated circuit design. For example, the IP is a hardware and/or software functional block for constituting the logic circuit of a semiconductor.
In SoC design, an On-Chip Network was introduced for data communication between IPs. The On-Chip Network has the same features of a computing network.
FIG. 1 is a block diagram illustrating an On-Chip Network where the present invention is applied. That is, FIG. 1 shows a typical On-Chip network having a switch.
As shown in FIG. 1, the On-Chip network includes a switch 10, OCN ports 20 each having an Up-sampler 21 and a down-sampler 22, and intellectual properties 30.
The switch 10 is a physical medium for receiving data from one IP through one OCN port and transferring the received data to the other IP through another OCN port. The up-sampler 21 of the OCN port 20 sequentially transfers data inputted from one IP to a switch. The down-sampler 22 of the OCN port 20 de-sequantializes data inputted from the switch and transfers the de-sequantialized data to the other IP.
Each of the IPs 30 is a circuit designed based on a protocol defined for the On-Chip network thereof. The IPs 30 are classified into master modules and slave modules according to the operating feature thereof in a chip.
As described above, the goal of On-Chip network is to enable IPs such as master modules and slave modules to communicate to each others in parallel. As shown in FIG. 1, the switch 10 is disposed to make them communicate in parallel.
FIG. 2 is a block diagram illustrating a switch of FIG. 1.
As shown in FIG. 2, the switch 10 of an On-Chip network includes an in-port 11, an arbiter 12, and a switch fabric 13.
The in-port 11 queues data inputted to the switch and requests the arbiter 12 to use the switch fabric 13. The arbiter 12 receives the request from the in-port 11 and gives a permission to use the switch fabric 13. The switch fabric 13 outputs data inputted from the in-port 11.
The On-Chip network enables a plurality of IPs to use the On-Chip network at the same time. That is, the switch of the On-Chip network decodes a tag included in data inputted from each IP, for example, a packet, and sequentially transfers the decoded data to a corresponding destination, a target IP. It will be described in more detail hereinafter.
The switch distributes data received from one IP over the On-Chip network in a unit of a packet although the received data is small or large. Also, the switch decodes the tag of each data to sequentially transfer the data to each destination although the data are distributed over the network. The tag of each data is a parameter indicating the origin and the destination of data.
Referring to FIG. 2, the switch receives a plurality of data having various destinations from different IPs through the in-port, and transfers the received data to corresponding destinations through the switch fabric according to the permission from the arbiter to use the switch fabric.
Conventionally, the arbiter accepts the request of the in-port and transfers data queued in the in-port to the switch fabric if the switch fabric is empty. That is, if the data transfer requests are received as many as the number of the arbiters as shown in FIG. 2, the corresponding number of data can be transferred to a destination thereof.
But, if only one master module is used like a conventional method which is a bus, the other slave modules must wait to use the On-Chip network until the master module finishes the communication with one slave module. Also, the other slave modules must wait for such a long time to transfer data to a corresponding destination although the other slave modules need transfer the small amount of data.
Such a solution degrades the data transmission parallelism rather than improves the data transmission parallelism on the On-Chip network. In order to improve the usability of the On-Chip network, it is better to distribute the data transmission operations to the other master modules or/and slave modules rather than concentrates the data transmission operations to one master module.
Therefore, it has been required to dispose a module in a slave module to improve the data communication parallelism between IPs on an On-Chip network and to reduce the concentration rate of using master modules in a circuit having less master modules and a plurality of slave modules.